Various signal transmission methods for transmitting data between elements of one device or between two or more devices have been developed.
FIG. 1 is a circuit diagram of a current mode logic (CML) system using a conventional signal transmission method. Specifically, FIG. 1 illustrates the transmission of a signal between a transmission unit TX of a first chip CP1 and a reception unit RX of a second chip CP2 via transmission lines TL and TLB. Referring to FIG. 1, output pads DQ1 and DQB1 of the transmission unit TX and output pads DQ2 and DQB2 of the reception unit RX are connected to termination resistors having a resistance of 50Ω, which can reduce or eliminate signal reflection.
The CML system 100 can transmit and receive signals using the same output pads by connecting the output pads DQ1 and DQB1 of the transmission unit TX of the first chip CP1 to a reception unit of the first chip CP1 and connecting the output pads DQ2 and DQB2 of the reception unit RX of the second chip CP2 to a transmission unit of the second chip CP2. This type of structure is called half-duplex.
Since the CML system 100 has a half-duplex structure, it can reduce the number of pins conventionally used for transmitting and receiving signals in half, can reduce signal reflection, and can achieve high operating speed. Thus, the CML system 100 may be used in a RAMBUS DRAM.
In the CML system 100, however, the output pads DQ1 and DQB1 are connected to the termination resistors having a resistance of 50Ω in parallel. Thus, the transmission unit TX may need a current Io of about 16 mA to maintain a voltage difference between a signal transmitted via the transmission line TL and a signal transmitted via the transmission line TLB at about 400 mV. In other words, the transmission unit TX or reception unit of the first chip CP1 or the transmission unit or reception unit RX of the second chip CP2 may use a considerable amount of power.
Another conventional signal transmission method is a low voltage differential signaling method in which a difference between the voltages of two transmission lines is transmitted as a signal. A low voltage differential signaling driver is widely used for various purposes, such as driving signals from a transmission unit to a reception unit. A low voltage differential signaling driver can quickly transmit signals even with low power and can have low electromagnetic interference (EMI) characteristics.
FIG. 2 is a circuit diagram of a conventional low voltage differential signaling driver 200. Referring to FIG. 2, the conventional low voltage differential signaling driver 200 includes a first chip CP1 and a second chip CP2. A transmission unit TX of the first chip CP1 includes a first current source IS1, which is connected to a power supply voltage VDD, a second current source IS2, which is connected to a ground voltage VSS, PMOS transistors TR1 and TR2, which are connected to the first current source IS1 in parallel, and NMOS transistors TR3 and TR4, which are connected to the second current source IS2 in parallel.
An input signal is applied to the transistors TR1 and TR3, and another input signal is applied to the transistors TR2 and TR4.
The first or second current source IS1 or IS2 is controlled so that two of the four transistors TR1, TR2, TR3, and TR4 can be turned on at the same time, thus generating a voltage at a termination resistor R. In order to let a current flow from a transmission line TL to a transmission line TLB via the termination resistor R, the transistors TR1 and TR4 should be turned on, and the transistors TR2 and TR3 should be turned off.
Since the termination resistor R may have a resistance of 100Ω, the transmission unit TX of the conventional low voltage differential signaling driver 200 may need a current Io of about 4 mA to maintain a difference of about 400 mV between the voltage of a signal transmitted via the transmission line TL and the voltage of a signal transmitted via the transmission line TLB. Accordingly, the conventional low voltage differential signaling driver 200 can consume a smaller amount of current than the CML system 100 of FIG. 1.
However, in the conventional low voltage differential signaling driver 200, unlike in the CML system 100 of FIG. 1, the termination resistor R may only be installed in a reception unit RX of the second chip CP2. Thus, the transmission unit TX of the first chip CP1 may suffer from signal reflections and severe noise.
In addition, such an asymmetry between the transmission unit TX of the first chip CP1 and the reception unit RX of the second chip CP2 may prevent the conventional low voltage differential signaling driver 200 from adopting a half-duplex structure. Thus, the number of pins used by the conventional low voltage differential signaling driver 200 to transmit and receive signals may increase.
FIG. 3A is a circuit diagram of another version of a conventional low voltage differential signaling driver 200 of FIG. 2, i.e., a conventional low voltage differential signaling driver 300, and FIG. 3B is a detailed circuit diagram illustrating an internal structure of the conventional low voltage differential signaling driver 300 of FIG. 3A. Referring to FIG. 3A, the conventional low voltage differential signaling driver 300 has the same structure as the conventional low voltage differential signaling driver 200 of FIG. 2 except that termination resistors R1 are installed in a transmission unit TX of a first chip CP1. Accordingly, the structure of the transmission unit TX of the first chip CP1 and the structure of a reception unit RX of a second chip CP2 are symmetrical, and thus the conventional low voltage differential signaling driver 300 can reduce signal reflections.
Referring to FIG. 3B, switches SW are turned on when the transmission unit TX of the first chip CP1 operates and are turned off when the reception unit RX of the second chip CP2 operates.
The termination resistors R1 each having a resistance of, for example, 50Ω are connected to each other in series in the transmission unit TX of the first chip CP1, and termination resistors R2 each having a resistance of, for example, 50Ω are connected to each other in series in a transmission unit TX of the second chip CP2. Thus, the structures of the transmission unit TX and a reception unit RX of the first chip CP1 and the structures of the transmission unit TX and a reception unit RX of the second chip CP2 are symmetrical, and thus, the conventional low voltage differential signaling driver 300 can reduce signal reflections and adopt a half-duplex structure.
In the conventional low voltage differential signaling driver 300, the termination resistors R1 and R2 are connected in parallel. Thus, the conventional low voltage differential signaling driver 300 has a total resistance of 50Ω. Accordingly, the transmission unit TX of the first or second chip CP1 or CP2 may need a current Io of about 8 mA to maintain a difference of about 400 mV between the voltage of a signal transmitted via a transmission line TL and the voltage of a signal transmitted via a transmission line TLB. Therefore, the conventional low voltage differential signaling driver 300 may consume a larger amount of current than the conventional low voltage differential signaling driver 200 of FIG. 2.